Semiconductor fabrication processes are often divided into three parts: a front end of line (FEOL), a middle of line (MOL) and a back end of line (BEOL). Front end of line processes include wafer preparation, isolation, well formation, gate patterning, spacers, and dopant implantation. Middle of line processes include gate and terminal contact formation. Back end of line processes include forming interconnects and dielectric layers for coupling to the FEOL devices.
These interconnects may be fabricated with damascene processes using plasma-enhanced chemical vapor deposition (PECVD) deposited interlayer dielectric (ILD) materials. These interconnect layers of semiconductor circuits have become smaller and more difficult to route because of the increased density of chip design. Because some materials that are used to connect various interconnect layers have higher resistance, this may affect the timing and/or resistance properties of these “vias” or electrical paths. As an example, tungsten is often used for vias between layers. The ratio of the depth to the diameter of a via is called the aspect ratio. Tungsten is often processed in a “single damascene” (SD) process to deposit or otherwise couple the tungsten material into the via. Copper is often processed in a “dual damascene” (DD) process.